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| N ANALOG - W DEVICES FEA TURES Precision Sample-and-Hold with 16-Channel Multiplexer III . 16 Single-Endedor 8 Differential Mode Control True 12-Bit Precision: Nonlinearity Channels with Switchable QO.005% OBS ~ High Speed: 1OilS Acquisition Time to 0.01% Complete and Calibrated: No Additional Parts Required Small, Reliable: 32 Pin Hermetic Metal DIP Versatile: Simple Interface to Popular Analog to Digital Converters High Differential Input Impedance (1010) and Common Mode Rejection (8OdB) Fully Protected Multiplexer Inputs PRODUCT DESCRIPTION The AD362 is a complete, precision 16-channel data acquisition system analog input section in hybrid integrated circuit form. Large-scale linear integrated circuitry, thick- and thinfilm technology and active laser trimming gives the AD362 extensive applications versatility along with full 12-bit accuracy. The AD362 contains two 9-channel multiplexers, a differential amplifier, a sample-and-hold with high-speed output amplifier, a channel address latch and control logic. The multiplexers may be connected to the differential amplifier in either an 8-channel differential or 16-channel single-ended configuration. A unique featUre of the AD362 is an internal user-controllable analog switch that connects the multiplexers in either a singleended or differential mode. This allows a single device to perform in either mode without hard-wire programming and permits a mixtUre of single-ended and differential sources to be interfaced by dynamically switching the input mode control. The sample-and-hold mode control is designed to connect direcdy to the "StatUs" output of an analog to digital converter so that a convert command to the ADC will automatically put the sample-and-hold into the "Hold" mode. A precision hold capacitor is included with each AD362. The AD362 output amplifier is capable of driving the unbuffered analog input of most high-speed, 12-bit successive-approximation ADCs. Interface is thereby reduced to two simple connections with no additional components required. When used with a 12-bit, 2S-microsecond ADC such as the ADS72, ADS74 or AD ADC80, system throughput rate is as high as 30kHz at full rated accuracy. The AD362KD is specified for operation over a 0 to +70C temperatUre range while the OLE AD362SD operates to specification from -55C to + 125C. Processing to MIL-STD-883 , Class B is available for the AD362SD. Both grades are packaged in a hermetic, electrostatically shielded 32-pin metal dual-in-line package. PRODUCT HIGHLIGHTS 1. The AD362, when used with a precision analog to digital converter, forms a complete, accurate, high-speed data acquisition system. 2. The 16-input channels may be configured in single-ended, differential or a mixtUre of both modes. Mode switching is provided by a user-controllable internal analog switch. 3. Multiplexers, differential amplifier, sample-and-hold and high-speed output buffer provide complete analog interfacing capabilities. 4. Internal channel address latches are provided to facilitate interfacing the AD362 to data, address or control buses. 5. All grades of the AD362 are hermetically sealed in rugged metal DIP packages. 6. A precision hold capacitor is provided with each AD362. 7. The AD362SD is specified over the entire military temperatUre range, -55C to +12SoC. Processing to MIL-STD883, Class B is available. TE ~ Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of parents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Route 1 Industrial Park; P.O. Box 280; Norwood, Mass. 02062 Tel: 617/329-4700 TWX: 710/394-6577 West Coast Mid-West Texas 714/842-1717 312/894-3300 214/231.5094 --- - (typical@+25C,:t15Vand+5V with 2000pF hold capacitorasprovided SPECIFICATIONS otherwisenoted) unless MODEL ANALOG INPUTS Number of Inputs Input Voltage Range, Linear Tmin to Tmax AD362KD 16 Single-Ended or 8 Differential (Electronically Selectable) :tIOV min :tSOnA max AD362SD/AD362SD-883BI * * * .t Input (Bias) Current, Per Channel Input Impedance On Channel. Off Channel Input Fault Current (Power Off or On) Common Mode Rejection Differential Mode Mux Crosstalk (Interchannel, Any Off Channel to Any On Channel) IOl0n, IOOpF 1010 n, IOpF 20mA, max, Internally Limited 70dB min (80dB typ) @ 1kHz, 20V pop -80dB max (-90dB typ) @ 1kHz, 20V p-p :t2.SmV mIX * * * * * * * * * * * * ACCURACY Gain Error, Tmin to Tmax Offset Error, Tmin to Tmax Linearity Error Tmin to Tmax TEMPERATURE COEFFICIENTS Gain, Tmill to Tmax Offset, :tlOV Range, Tmin to Tmax SAMPLE AND HOLD DYNAMICS ApertUre Delay Aperture Uncertainty Acquisition Time, for 20V Step to :to.01 % of Final Value Feedthrough Droop Rate DIGIT AL INPUT SIGNALS2 Input Channel Select (Pins 28-31) Channel Select Latch (Pin 32) OBS Noise Error Tmin to Tmax Offset, Channel to Channel :to.02% FSR, max :t4mV :to.005% max :to.Ol% max ImV pop, 0.1 to IMHz, mIX 2m V p-p, 0.1 to 1MHz, mIX :t4ppm/C max :t2ppm/ C max lOOns max (SOns typ) SOOpsmIX (lOOps typ) 18J.LSmax (lO~s typ) -70dB max (-80dB typ) @ 1kHz 2mV/ms max (lmV/ms typ) OLE * * * * * * * * * * * * * * * * * * * * :t2ppm/ C max :t1.Sppm/oC mIX TE 8~ 4-Bit Binary, Channel Address lLS TTL Load "I ": Latch Transparent "0": Latched 8LS TTL Loads "0": Single-Ended Mode "I ": Differential Mode 3TTL Loads "0": Sample Mode "I ": Hold Mode 1TTL Load +ISV, :!:S% @ 30mA mix -ISV, :!:S% @ 30mA mix +SV, :tS% @ 40mA mix 1.1 Watts mix Single Ended/Differential Mode Select (Pin 1) Sample and Hold Command (Pin 13) POWER REQUIREMENTS Supply Voltages/Currents Total Power Dissipation TEMPERATURE RANGE Specification Storage NOTES: 1 0 to +700C -SSoC to +8S0C3 -SSoC to +12SoC -SSoC to +IS0C The AD362 is available full;' processed and screened to the requirements of MIL-STD-883, Class B. A complete list of tests is given on page 3. When ordering, specify "AD362SD/883B". 8 ~ 2 One TTL Load is defmed as IlL =-1.6mA mIX @ VIL =O.4V, IB-I=40I1A mIX @ VB-I =2.4V. One LSTTL Load is defined as IIL=~.36rnA max@ VIL=O.4V,lrn=20I1A max@ Vrn=2.7V. 3 AD362KD External Hold Capacitor is limited to +8SoC; AD362 device itself may be stored at up to +lS0C. subject to change without notice. Specifications -2- ~" t ; I ABSOLUTE MAXIMUM RATINGS (ALL MODELS) +V,DigitaISupply +V, Analog Supply -V, Analog Supply +5.5V +16V -16V :tV, Analog Supply 0 to +V, Digital Supply :t1V , Pin Number 1 ---Function Single-End/Differential Mode Select "0": Single-Ended Mode "1": Differential Mode Digital Ground Positive Digital Power Supply, +5V "High" Analog Input, Channel 7 "High" Analog Input, Channel 6 "High" Analog Input, Channel 5 "High" Analog Input, Channel 4 "High" Analog Input, Channel 3 "High" Analog Input, Channel 2 "High" Analog Input, Channell "High" Analog Input, Channel 0 Hold Capacitor (Provided) Sample-Hold Command "0": Sample Mode "1": Hold Mode ! VIN, Signal i VlN, Digital , AcND to DGND 2 , I I i 1 3 4 5 6 7 8 9 PROCESSING FOR HIGH RELIABILITY I OBS PROCESS CONDITIONS 1) 100% pre-cap Visual Inspection Bake In-house Criteria 2) Stabilization 24 hours @ +lS0C 3) Seal Test, Gross Leak 4) Operating Bum-In 24 hours@+12SoC PROCESSING TO MIL-STD-883 STANDARD PROCESSING As part of the standard manufacturing procedure, all models of rhe AD362 receive the following processing: ~ I 110 Method 1014 Test Condition C t All models of AD362 ordered to the requirements of MIL-STD-883. Method 5008 are identified with a /883B suffix and receive the following processing: PROCESS 1) 100% pre-cap Visual Inspection 2) Stabilization 3) Temperature Bake Cycle CONDITIONS 2017.1 1008, 24 hours @ +lS0C OLE 1 11 12 13 I I i 14 15 16 1010, Test Condition C, 10 cycles, -65C to +lS0C 2001, VI Plane, 1000G Visable Damage 1015, Test Condition B 160 hours @ +12SoC 1014, Test Condition A, 5 x 10-7 std cc/sec 1014, Condition C Per Data Sheet 2009 4) Constant Acceleration 5) Visual Inspection 6) Operating Burn-In 7) Seal Test: Fine Leak Gross Leak 17 18 19 20 21 22 23 24 25 26 27 28 29 30 8) Final Electrical Test 9) External Visual Inspection l -3-- Normally Connected to ADC StatUs Offset Adjust (See Figure 5) Offset Adjust (See Figure 5) Analog Output Normally Connected to ADC "Analog In': Analog Ground "High" ("Low") Analog Input, Channel "High" ("Low") Analog Input, Channel Negative Analog Power Supply, -15V Positive Analog Power Supply, +15V "High" ("Low") Analog Input, Channel "High" ("Low") Analog Input, Channel "High" ("Low") Analog Input, Channel "High" ("Low") Analog Input, Channel "High" ("Low") Analog Input, Channel "High" ("Low") Analog Input, Channel Input Channel Select, Address Bit AE Input Channel Select, Address Bit AO Input Channel Select, Address Bit Al Input Channel Select, Address Bit A2 Input Channel Select Latch "0": Latched "1": Latch Transparent TE 15 (7) 14 (6) 13 12 11 10 9 8 (5) (4) (3) (2) (1) (0) (100+) $119.50 $230.00 $280.00 AD362 ORDERING GUIDE Specification Temp Range 0 to +70C -55C to +125C -55C to +125C Max Gain TC :t4ppm/C :t2ppm/ C :t2ppm/C Prices (25-99) $139.50 $270.00 $330.00 Model (1-24) $160.00 $295.00 $365.00 8 AD362KD AD362SD AD362SD/ 883B NOTE: D Suffix --= Dual-In-Line package designator. -- ----\.0362 DESIGN rhe AD362 consists of two 8-channel multiplexers, a differen:ial amplifier, a sample-and-hold with high-speed output buf:er, channel address latches and control logic as shown in ~igure 1. The multiplexers can be connected to the differential lmplifier in either an 8-channel differential or 16-channel ;ingle-ended configuration. A unique fearure of the AD362 is In internal analog switch controlled by a digital input that Jerforms switching between single-ended and differential nodes. This fearure allows a single AD362 to perform in ~ither mode without external hard-wire interconnections. Of more significance is the ability to serve a mixtUre of both ;ingle-ended and differential sources with a single AD362 by :Iynamically switching the input mode control. '"'GW' A.ACOG '.PUTS smaller capacitor will allow faster sample-and-hold response but will decrease accuracy while a larger capacitor will increase accuracy at slower conversion rates. The output buffer is a high speed amplifier whose output impedance remains low and constant at high frequencies. Therefore, the AD362 may drive a fast, unbuffered, precision ADC without loss of accuracy. The AD362 is constructed on a substrate that includes thickfilm resistors for non-critical applications such as input protection and biasing. A separately-mounted laser-trimmed thinfilm resistor network is used to establish accurate gain and high common-mode rejection. The metal package affords electromagnetic and electrostatic shielding and is hermetically welded at low temperatures. Welding eliminates the possibility of contamination from solder particles or flux while low temperatUre sealing maintains the accuracy of the laser-trimmed thin-film resistors. THEORY OF OPERATION Concept The AD362 is intended to be used in conjunction with a highspeed precision analog-to-digital converter to form a complete data acquisition system (DAS) in microcircuit form. Figure 2 shows a general AD362-with-ADC DAS application. AO362 I- OBS 1 r ..'OW.. ANACOG 'NPUTS ONPU' '"ANNEL "LEO' '"ANNEL "LEO' ",," Figure 1. A0362 Analog Input Section Functional Block Diagram and Pinout Multiplexer channel address inputs are interfaced through a level-triggered ("transparent") input register. With a Logic "1" at the Channel Select Latch input, the address signals feed through the register to directly select the appropriate input channel. This address information can be held in the register by placing a Logic "0" on the Channel Select Latch input. Inrernallogic monitors the status of the Single-Ended/Differential lode inp ..of I J , J '""""'" ~O"."'ON ,,",,"" :{ Figure 2. AD362 with ADC as a Complete Data Acquisition System TE """,, ,m '"' 88 . differential amplifier buffers the multiplexer outputs while roviding high input impedance in b0th differential and. singlei1ded modes. Amplifier gain and common mode rejection are ctively laser-trimmed. lhe sample-and-hold is a high speed monolithic device that can also function as a gated operational amplifier. Its uncommitted differential inputs allow it to serve a second role as the output subtractor in the differential amplifier. This eliminates one amplifier and decreases drift, settling time and power consumption. A Logic "1" on the Sample-and-Hold Command input will cause the sample-and-hold to "freeze" the analog signal while the ADC performs the conversion. Normally the Sampleand-Hold Command is connected to th~ ADC Status output which is at Logic" 1" during conversion and Logic "0" between conversions. For slowly-changing inputs, throughput speed may be increased by grounding the Sample-and-Hold Command input instead of connecting it to the ADC status. A Polystyrene hold capacitor is provided with each commercial temperatUre range device (AD362KD) while a Teflon capacitor is provided with units intended for operation at temperatures up to 125C (AD362SD). Use of an external capacitor allows the user to make his own speed/accuracy tradeoff; a By dividing the data acquisition task into two sections, several important advantages are realized. Performance of each design is optimized for its specific function. Production yields are increased thus decreasing costs. Furthermore, the standard configuration packages plug into standard sockets and are easier to handle than larger packages with higher pin counts. Svstem Timine: Figure 3 is a timing diagram for the AD362 connected as shown in Figure 2 and operating at maximum conversion rate. The ADC is assumed to be a conventional 12 bit type such as the AD572 or AD ADC80. ADDRESS ADDRESS lATCH ~ CONVERT COMMAND STATUS {SAMPlE.HOlD) ,. Figure 3. DAS Timing Diagram GATED CLOCK -4-- - . . The normal sequence of events is as follows: 1. The appropriate Channel Select Address is latched into the address register. Time is allowed for the multiplexers to settle. 2. A Convert Start command is issued to the ADC which, in response, indicates that it is "busy" by placing a Logic "1" on its Status line. 3. The ADC Status controls the sample-and-hold. When the ADC is"busy", the sample-and-hold is in the Hold mode. 4. The ADC goes into its conversion routine. Since the sampleand-hold is holding the proper analog value, the address may be updated during conversion. Thus multiplexer settling time can coincide with conversion and need not affect throughput rate. 5. The ADC indicates completion of its conversion by returning Status to Logic "0". The sample-and-hold returns to the Sample mode. 2. Trigger the oscilloscope on Status. Delay the display such that Status is mid-screen. 3. Observe the LSB data output of the ADC. 4. Vary the analog input control to confirm that the LSB transition precedes the Status transition. Sin~le-Ended/Differential Mode Control The AD362 features an internal analog switch that configures the Analog Input Section in either a 16-channel single-ended or 8-channel differential mode. This switch is controlled by a TTL logic input applied to pin 1 of the Analog Input Section: "0": Single-Ended (16 channels) "1 ": Differential (8 channels) When in the differential mode, a differential source may be applied between corresponding "High" and "Low" analog input channels. It is possible to mix SE and DIFF inputs by using the mode control to command the appropriate mode. In this case, four microseconds must be allowed for the output of the Analog Input Section to settle to within :to.OI % of its final value, but if the mode is switched concurrent with changing the channel address, no significant additional delay is introduced. The effect of this delay may be eliminated by changing modes while a conversion is in progress (with the sample-and-hold in the "Hold" mode). When SE and DIFF signals are being processed concurrently, the DIFF signals must be applied between corresponding "High" and "Low" analog input channels. Another application of this feature is the capability of measuring 16 sources individually andlor measuring differences between pairs of those sources. Input Channel Addressin~ Table 1 is the truth table for input channel addressing in both the single-ended and differential modes. The 16 single-ended channels may be addressed by applying the corresponding digital number to the four Input Chanl1el Select address bits, AE, AD, AI, A2 (pins 28-31). In the differential mode, the eight channels are addressed by applying the appropriate digital code to AD, Al and A2; AE must be enabled with a Logic "1 ". Internal logic monitors the status of the SE/DIFF Mode input and addresses the multiplexers singularly or in pairs as required. ADDRESS AE A2 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ON ---------- (Pin Number) CHANNEL Ended 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ~ OBS +15V 51<" ANALOG INPUT 6. If the input signal has changed full-scale (different channels may have widely-varying data) the sample-and-hold will typically require 10 microseconds to "acquire" the next input to sufficient accuracy for 12-bit conversion. Mter allowing a suitable interval for the sample-and-hold to stabilize at its new value, another Convert Start command may be issued to the ADC. MSB BIT 2 LSB g~G,'lAL OUTPUTS I 20"" jf I : 51<" ADC UNDER TEST OLE 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 --...-1 -15V STATUS TE Differential "Hi" "La" None None ~~ None None None None None (11) (10) (9) (8) (7) (6) (5) (11) (10) m (8) (7) (6) (5) (4) (27) (26) (25) (24) (23) (22) (19) 0 1 2 3 4 5 6 0 (27) 1 (26) 2 (25) 3 (24) 5 (23) 5 (22) 6 (19) 7 (18) CHANNEL A "1"~ "STATUS" "o"_'_~ CHANNEL "LSB" B I I I , : VALID DATA I 'I --. I .--STATUSDELAY Figure4. ADC Status Valid Test NOTE: Valid OutPut Data Not all ADCs have all data bits available when Status indicates that the conversion is complete. Successive approximation ADCs based on the 250213/4 type of register must have a Status delay built in or the final data bit will lag Status by approximately SOns. This will result in two problems: 1. The sample-and-hold will return to Sample, disturbing the analog input to the ADC as it is attempting to convert the least significant bit. This may result in an error. 2. If the falling edge of Status is being used to load the data into a register, the least significant bit will not be valid when loaded. An external lOOns delay or use of an ADC with a valid Status output is necessary to prevent this problem. The applications shown in this data sheet ensure that all data bits will be valid. The following test may be made to determine if the ADC Status timing is correct: 1. Connect the ADC under test as shown in Figure 4. . ! ~-Q~l 7 ~4)_- Table 1. Input Channel Addressing Truth Table -5---- When the channel address is changed, six microseconds must be allowed for the Analog Input Section to settle to within :to.Ol % of its final output (including settling times of all elements in the signal path). The effect of this delay may be eliminated by performing the address change while a conversion is in progress (with the sample-and-hold in the "Hold" mode). Inout Channel Address Latch The AD362 is equipped with a latch for the Input Channel Select address bits. If the Latch Control pin (pin 32) is at Logic "1 ", input channel select address information is passed through to the multiplexers. A Logic "0" "freezes" the input channeraddress present at the inputs at the "1"-to-"O" transition (level-triggered). This feature is useful when input channel address information is provided from an address, data or control bus that may be required to serv:ce many devices. The ability to latch an address is helpful whenever the user has no control of when address information may change. Samole-and-Hold Mode Control The Sample-and-Hold Mode Control input (pin 13) is normally connected to the Status output (pin 20) from an analog to digital converter. When a conversion is initiated by applying a Convert Start command to the ADC, Status goes to Logic" 1", putting the sample-and-hold into the "Hold" mode. This "freezes" the information to be digitized for the period of conversion. When the conversion is complete, Status returns to Logic "0" and the sample-and-hold returns to the "Sample" mode. Eighteen microseconds must be allowed for the sampleand-hold to acquire ("catch up" to) the analog input to within :to.Ol % of the final value before a new Convert Start command is issued. The purpose of a sample-and-hold is to "stop" fast changing input signals long enough to be converted. In this application, it also allows the user to change channels and/or SEt DIFF mode while a conversion is in progress thus eliminating the effects of multiplexer, analog switch and differential amplifier settling times. If maximum throughput rate is required for slowly changing signals, the Sample-and-Hold Mode Control may be wired to ground (Logic "0") rather than to ADC ,tatus thus leaving the sample-and-hold in a continuous ;ample mode. lold Caoacitor \ 2000pF capacitor is provided with each AD362. One side )f this capacitor is wired to pin 12, the other to analog ground as close to pin 17 as possible. The capacitor provided with the AD362KD is Polystyrene while the wider operating temperature range of the AD362SD requires a Teflon capacitor (supplied). Smaller capacitors will allow slightly faster operation, but only with increased noise and decreased precision. 1000pF will typically allow acquisition to 0.1 % in four microseconds. Larger capacitors may be substituted to reduce noise, and sample-to-hold offset, but acquisition time of the sample-andhold will be extended. If less than 12 bits of accuracy is required, a smaller capacitor may be used. This will shorten the S/H acquisition time. In all cases, the proper capacitor dielectric must be used; i.e., Polystyrene (AD326KD only) or Teflon (AD362KD or SD). Other types of capacitors may have higher dielectric absorption (memory) and will cause errors. CAUTION: Polystyrene capacitors will be destroyed if subjected to temperatures above +850 C. No capacitor is required if the sample-and-hold is not used. Analo!! Inout Section Offset Adjust Circuit Although the offset voltage of the AD362 may be adjusted, that adjustment is normally performed at the ADC. In some special applications, however, it may be helpful to adjust the offset of the Analog Input Section. An example of such a case would be if the input signals were small 10mV) relative to AD362 voltage offset and gain was to be inserted between the AD362 and the ADC. To adjust the offset of the AD362, the circuit shown in Figure 5 is recommended. AD362 ANALOG INPUT SECTION 1 . 8 . OUTPUT 16 OBS Figure 5. AD362 Offset Voltage Adjustment Under normal conditions, all calibration is performed at the ADC Section. Other Considerations OLE AD362 DGND TO CARD CONNECTOR Grounding: Analog and digital signal grounds should be kept separate where possible to prevent digital signals from flowing in the analog ground circuit and inducing spurious analog signal noise. Analog Ground (pin 17) and Digital Ground (pin 2) are not connected internally; these pins must be connected externally for the system to operate properly. Preferably, this connection is made at only one point, as close to the AD362 as possible. The case is connected internally to Digital Ground to provide good electrostatic shielding. If the grounds are not tied common on the same card with the AD362, the digital and analog grounds should be connected locally with back-toback general-purpose diodes as shown in Figure 6. This will protect the AD362 from possible damage caused by voltages in excess of :tl volt between the ground systems which could occur if the key grounding card should be removed from the overall system. The device will operate properly with as much as :t200m V between grounds, however this difference will be reflected directly as an input offset voltage. TE ADC AGND 88 Figure 6. Ground-Fault Protection Diodes Power Supply Bypassing: The :t15V and +5V power leads should be capacitively bypassed to Analog Ground and Digital Ground respectivelyfor optimum device performance. IJ.LF tantalum types are recommended; these capacitors should be located close to the system. It is not necessary to shunt these capacitors with disc capacitors to provide additional high frequency power supply decoupling since each power lead is bypassed internally with a 0.039J.LFceramic capacitor. , . -6- - "" ~,:~:2~~-~!:.~ :~~,~ ~ - "'~f':: ~ 4 Interfacing to Popular Analog to Digital Converters The AD362 has been designed to interface directly to most analog to digital converters; often no additional components are required and only two interconnections must be made. The direct interface requirements for the ADC are as follows: 1. The ADC StatUs output must be positive-true Logic ("1" during conversion). 2. Transition from "0" to "1" must occur at least 200ns before the most significant bit decision is made (successive approximation ADC) or before input integration starts (integrating type ADC). 3. StatUs must not retUrn to "0" before the LSB decision is made (see page 5). 4. If StatUs is being used to latch output data, it must not retUrn to Logic "0" until all output data bits are valid and available. Figure 7a shows the AD362 driving an AD ADC80. The AD ADC80 is a 12-bit, 25-microsecond, low-cost ADC that meets all of the requirements listed above. Throughput rate is typically 30kHz with no missing codes over the operating temperatUre range. Figure 7b shows a lO-bit application based on the AD362 and the AD571, a complete low cost 10-bit, 25-microsecond ADC. In this case, two of the above requirements are not met: 1. DR (DATA READY), as StatUs, is positive-true but. . . 2. DR does not indicate that a conversion is in progress until 1.5JJs after conversion starts. 3. DR does indicate conversion complete after the LSB decision is made, but. . . 4. DR precedes the enabling of the AD571 output 3-state gates by 500ns. The gating provided by Ul allows the applied convert com-mand (CC) to initiate input hold at the AD362. CC must last for more than 1.5JJs so that DR may then assume control of Hold. If conversion is continuous (consistent with multichannel operation), the next convert command can be used to load the previously-converted data into an output register. For single conversion operation, a IJJs delay of the falling edge of DR may be used to signify valid data. DC POWER OBS ANALOG INPUTS 1161 DC POWER Complete system throughput performance is determined by combining the worst-case specifications of the AD362 and the ADC. If guaranteed system performance is required, the AD363 and AD364 are recommended. The AD363 includes an AD362 and an AD572 12-bit, 25-microsecond precision ADC. The AD364 consists of an AD362 and an AD574 12-bit, microprocessor-compatible, low cost ADC. Each is specified as a complete, two-package system; data sheets are available upon request. OLE ANALOG INPUTS (IS) CAPACITOR AOJ62 HOLD I IANALOG ANALOG ADAOC80 OUT IN 0 TE DATA BITS OUT (101 AO571 BITS OUT (12) DATA DR Me' CHANNEL SELECT LATCH SAMPLE/HOLD I I STATUSOUTPUT CHANNEl SELECT LATCH CONVERT START .n. DATAOUTPUT STROBE ITO REGISTERI CONVERT COMMAND 1/474LSJ2 ~1.5~. --::J C MIN DATA STROBE (TO OUTPUT REGISTER) a. l2-Bit DAS Using AD362 and AD ADC80 b. la-Bit DAS UsingAD362 and AD571 Figure 7. Data Acquisition Systems Based on the AD362 and Popular ADC's I -7- Interfacing to Special Purpose ADCs The ADS200 series of ADCs perform a 12-bit conversion in SO microseconds and feature totally adjustment-free operation, high accuracy, and a small hermetically-sealed 24-pin package. These ADCs are often used in high-reliability applications and, like the AD362SD (which operates over the -SSoC to +12SoC temperature range) are available processed to MILSTD-883, Class B. The ADS200 series meets all of the interfacing requirements for direct connection to the AD362 as shown in Figure 8a. System throughput rate is typically 16kHz. DC POWER The HAS series of ultra-fast ADCs are 8-bit (HAS080l), 10bit (HASI00l) and 12-bit (HASI202) devices that convert in I.S, 1.7, and 2.8 microseconds (maximum) respectively. These devices are hybrid IC's, packaged in 32-pin DIPs. Since the Data Ready signal from the HAS precedes the LSB decision, DR must be delayed. Figure 8b shows the appropriate circuitry to provide that delay. Throughput rate for the 12-bit system is typically 80kHz. DC POWER 8 HOLD ANALOG INPUTS 116) DATA BITS OUT 112) AD362 7CAPACI ANALOG OUT TOR ANALOG IN HAS SERIES DATA BITS OUT 18. 10 OR 12) 0 CXI ..... M I C) I N 18 u SAMPLE/HOLD DR ANALOG INPUTS (161 OBS AD5200 SERIES STATUS OUTPUT ENCODE COMMAND DATA STROBE (TO OUTPUT REGISTER) INPUT CHANNEL r 1 ---0 4, I 'c", 1oopF C~:L~~~L SL~L,~g Jl CLOCK INPUT CONVERT START DATA STROBE ITO OUTPUT REGISTER) a. 12-Bit High Accuracy and Reliability AD362 and AD5200 DAS Using Figure B. Data Acquisition Systems Based on the AD362 and Purpose ADCs OLE CONVERT COMMAND 14) r---J I IT I I I : 1- --:J .~150ps C MIN I ~- - - ~~v-.:'~~T U1:7400 ":'...J J I b. High-Speed DAS Using AD362 and HAS OUTLINE DIMENSIONS PACKAGE SPECIFICATIONS Dimensions shown in inches and (mm). TE 8 "D" PACKAGE 1.00 125.4) MIN C==J MODEL DESIGNATION IKD OR SO) HOLD CAPACITOR 0.69 117.5) MAX I CAD362 rnn__~__n_n_n; .8 PIN 1./ INDENTIFIER 0.358.9) 1 --I MAX I } f-- - DATE CODE 0 I 'THIS DIMENSION IS FOR POL YSTYRENE CAPACITOR SUPPLIED WITH AD362KD MAX BODY LENGTH OF TEFLON CAPACITOR SUPPLIED WITH AD362SD IS 1.00". .I. --1~ 0211531 T t ~ GREEN~""" GLASS BEAD PIN 1, I. C; 000 00 (~i, 0000 0000 -(-L T ..1 0 I 0.025 10.46.0.05) 0.018 YP 0.2015.11 IA.0.00~ D !T 1 0.900 -- t 1 10.6) - ~-L T (~662) 0 0 -L GLASS BEAD STANDOFFS 0.0812.01 DIA.TYP-I --J 0 0 00 L ,00 00 0000000 00 0.100. TYP 12.51 T 1 I~~) 122.9)-1 ~ CI! ::> z 0 w IZ a: a.. METAL 32 PIN DUAL.IN.LINE PACKAGE NOTES: 11 PACKAGE: KOVAR WITH 100pIN. MIN., NICKEL PLATE 2) PINS: KOVAR WITH 50p1N. MIN 24K GOLD PLATE 3) PACKAGE AND PINS MEET ALL REQUIREMENTS OF MIL-STD-883 41 TOLERANCES, UNLESS OTHERWISE NOTED: al .XX: '.01 1.25) h) .XXX: '.005 1.13) MATING SOCKET: ROBINSDN.NUGENT PART NUMBER SB.16.G 12 REQUIRED) ROBINSON.NUGENT, INC. 800 EAST EIGHTH STREET NEW ALBANY, IN 47150 1812) 945-0211 8 -8- |
Price & Availability of AD362SD
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